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Responsibilities:
Participate in the design and implementation of the leading edge, front-end or back-end ASIC design flow which covers from logical design to physical implementation
Participate in the research of Design Methodology to improve automation and productivity
Work closely with design team for projects’ Tapeout
Requirements:
Major in CS, EE or related, master or bachelor degree.
Knowledge of ASIC design (Digital circuit design, verilogHDL) is required
Be familiar with Linux working environment
Experience in program with one or more languages (CShell, TCL, Perl or python etc.) is a plus
Experience in any ASIC flow and/or EDA tools is a plus
Good in English writing and speaking
Be eager to learn new knowledge, be able to resolve complex problem.