[上海]美满电子科技（上海）有限公司

职能类别:大学/大专应届毕业生

Job Description 
Candidates will be involved in the whole ASIC design flow from RTL coding through P&R support, which includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing analysis and sign-off. Candidates will work with architecturer to implement different switch feature, and work with verification engineer to debug the failed case. Candidates will also work closely with analog design teams on IP integration, with P&R engineers on chip floor planning and timing optimization, and with product/test engineers on ATE tests. Work closely with frontend and backend design teams, as well as test engineers.  Participate in logic design in SOHO switch/PHY chips and ASICs.  Perform logic synthesis, floor planning, timing analysis and timing signoff for chip tapeout. Work on DFT designs including MBIST, EDT, OCC, JTAG. Run Mentor and Synopsys tools to create and verify ATPG patterns. Work with test engineers to build up and debug test programs.

Job Requirement
-Master degree
-Hand-on experience in RTL design

-Experience in running EDA tools of simulation, synthesis, timing analysis and formal verification
-Solid knowledge and background in ASIC development
-Good communication skills

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