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As a result of the improvement in chip process, design scale and performance/power ratio expectation, physical design for digital chips have huge challenges on high frequency, low power, multiple application modes etc. Effective and high quality implementation of building chips is the guarantee of the company’s competitiveness.
As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. You will face the biggest challenge based on the most advanced processes on building chips in the world.
RESPONSIBILITIES:
?Chip integration and netlist generation
?Synthesis
?RTL/netlist quality check
?Formal Verification
?Constraints creation and validation, timing budget.
?Work with ASIC team to analyze/resolve special timing issues.
?Co-work with PR engineers to implement chip partition and floorplan
?Work in conjunction with RR engineers to achieve timing closure for both partition and full chip level
?Achieve special mode timing closure, such as io, test, clock etc.
?Function eco creation
?Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout)
?Flow automation development for above areas
?Methodology in any of above areas.
MINIMUM REQUIREMENTS:
?BSEE, MSEE is preferred
?Project experience in IC design implementation
?Courses taken in circuit design, digital design
?Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is preferred
?Proficient user of Perl or TCL is preferred
?Excellent English communication skill