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Responsibilities 岗位职责:
-Main resposible on IP level, subsystem level and SoC level verification for connectivity MCU, MPU which targets IoT application. the verification work includes develop test benches, modeling, assertions/checkers/monitors, test plan and test development and sign off for tape out.
-Support the IP and SoC design, architecture definition.
-Join the verification methodology innovation.
Requirements 任职要求:
-Bachelor or master degree, majoring in microeletronics, electronic engineering , computer science or relevant disciplines.
-Good language skill in English, passed CET-6.
-Have knowledge about EDA simulation and synthesis tool as well as VLSI design flow.
-Good knowledge in Verilog, VHDL, System Verilog, and script language.
-Good knowledge in RTL code style, full synchronous design style, and knowledge of Design-for-Test (DFT) is a plus.
-Complex IP/ SOC Design Verification, direct experience in IP/SOC or Wireless MAC/Tranceiver (BLE, Zigbee,Wi-Fi,NFC),or Industry bus standard (PCI-e, USB) is preferred
-Have used Unix/Linux system and EDA tool from Cadence, Synopsis, Mentor digital and/or analog development.
-Have knowledge about computer architecture, 8bit, 16bit or 32bit Micro-controller or Micro-processer is a plus.
-Have knowledge of OVM,VMM or UVM is a plus.
-Have knowledge of Wireless communication ,DSP is a plus.
-Prefer know-how of ARM or AHB bus system.
-Prefer experience of formal verification with property scheme, for example SVA (System Verilog Assertion).