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Responsibilities 岗位职责:
-Participate in definition of both chip level and block level design-for-test structure and methodology
-Responsible for ATPG and model creation, memory Built in Self Test, Embedded -Deterministic Test and Boundary Scan Test
-Work closely with design engineer for design optimization for test coverage improvement, test volumn and test time reduction
-Responsbile for scan/bist pattern simulation based on timing files and gate-level netlist.
-Work closely with Test Engineer to debug and solve scan/bist pattern failures on tester
-Work as a global team to do complex SOC design and test
Requirements 任职要求:
-Master Degree or equivalent from Electronic, Electrical or Computer Science.
-Good team work spirit and communication skill.
-Good language skill in English, Pass CET-6.
-Good knowledge in Verilog or VHDL.
-Good knowledge in System-Verilog is a plus.
-Have used Unix/Linux system and EDA tool from Cadence, Synopsis, Mentor digital and/or analog developing.
-Basic knowledge of MBIST, Scan is a plus.
-Good knowledge of IC design flow is a plus, including RTL coding, simulation, verification, synthesis and STA;
-Understanding of testers and associated hardware is a plus;
-Familiar with Shell/TCL/Perl grogram is a plus;