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岗位职责:
1 Develop RTL code for Block / IP or SoC top level
2 Working with project lead to define FEINT flow setting, including synthesis, equivalence check flow. Define frequency target, power strategy and etc.
3 Regular run FEINT flow, check quality, drive/co-work IP team on issue solving and QoR improvement.
4 Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc.
专业要求:EE, CS, or related