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Responsibilities
- Main responsibility is to support analog design team demands in layout design, physical verification(DRC/LVS), technology study, contact window with backend team
- Responsible for analog IP layout, LEF, floor plan, digital code hardening
- Communicate with analog design engineers to ensure high quality
Requirements:
- Master degree
- Must have a good understanding of basic analog circuits, cmos process
- Familiar with cadence virtuoso and caliber verification tools. Experience in skill coding is a plus
- Must have a good communication skills, English reading and writing skills
Location: Suzhou