[上海]amd2011招聘

amd大量招人,招asic 方面的，design和verification，还有一些软件和硬件系统等工程师职位和manager职位，有意向的发简历到 jane2.jin@

或者联系msn:  jj_seu@   qq:1317656040

职位就是如下几个职位； Staff/Sr/ GPU ASIC Integration Engineer  ；Sr ASIC Design Engineer；Senior. Design Verification Engineer 

MTS/Sr. ASIC Engineer:
 
 
 
 
 

 
 
 
   

      
Position Summary

- Participate IP and SoC level architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.

- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.

- Go through the FE design flow to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.

- Write ASIC specific part of test plan. Prove functional correctness from block level to SoC level

- Support FW/SW bring-up and debugging

- Working as the technical point of contact on the ASIC area.

- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.

                                         

Essential Functions:

RTL, Verification, Testbench, SystemC, SystemVerilog, OVM

Essential Requirements/Qualifications:

- Proven ASIC / SoC Design / Verification Experience

- Must have strong background on IP development

Desired:

- Major in EE & CS

- Must be proficient in Verilog coding, debugging and modeling

- Should be familiar with Advanced C/C++/SystemVerilog, RTL coding techniques.

- PCIe, BIOS, ACPI experience would be an asset.

- Must be familiar with Design for verification Methodology (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)

- Should be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.

- Must be familiar with shell/perl/tcl programming in linux OS.

- Should have strong problem solving skills

- Good English hearing, speaking, reading and writing capabilities.

- Good communication skills

- Will be a big plus if having mass production tape‐out experience.

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