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Description
As anIC Layout Design Engineer at Micron's Shanghai Design Center, you will work ina highly innovative and motivated design team using state of the art memorytechnologies to advance DRAM Memory design.
Aspart of a multi-disciplinary team, you will contribute to physical layout floorplan of various memory chip circuit blocks, and perform block level layout,LVS/DRC verification and using other CAD tools to check layout.
Ofcourse you will also work closely with Micron's various design teams in US andother countries and leverage vast resources available throughout Micron’sglobal sites. Additionally, you will perform verification (LVS/DRC etc) oflayout to the full-chip level, and assist in project tape out.
Requirements for Intern:
College degree (or above) in Integrated Circuit Design and ElectricalEngineering or other related engineering field.
Willingto develop his/her future career in IC layout
Hands-onand willing to learn
Familiarwith Cadence OA and Calibre verification tools is a plus.
Understandingof basic CMOS circuits is a plus.
Scorerequirement: passed all the tests not including makeup score.
Englishlanguage skill in writing and speaking.
CET4 score above 425 is a plus.
Hasgood communication and team work spirit
Can presentat duty 3-5 days per week