- 工作地点：上海
- 职位：ASIC Design Verification Engineer（上海）
- 信息来源：前程无忧(51JOB)
说明：
职能类别:大学/大专应届毕业生
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Responsibilities:
Understand the ASIC design/verification flow and help design/verification engineers to accomplish targets.
Develop infrastructure and environment for IP/SoC level design verification.
Closely working with Design/Architecture/Verification team to develop new verification component.
Requirements:
Major in Electrical Engineering, Computer Science or related
Good understanding on ASIC design verification flow
Good design verification experience
Programming knowledge on Verilog/SystemVerilog, C/C++
Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
Should have good communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
Strong problem solving skills
公司简要介绍：
公司名称:超威半导体（上海）有限公司
公司类型:外资（欧美）
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