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Responsibilities:
Implement DFT features including SCAN, Boundary SCAN, MBIST, Analog Macro test logic and etc.
Generate and verify DFT structural patterns and functional patterns.
Generate DFT related timing constraints and work with PD team for timing closure.
Participate in ATE bring-up and debug the DFT patterns on ATE.
Requirements:
Understand General ASIC design flow.
Good Knowledge of script language, such as Tcl, Shell, Perl.
Strong problem solving skills.
Good written and oral English.
Good communication skills.
Hands on experience on ASIC DFT design and verification preferred.