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Responsibilities:
Closely Working with global IP design team and SOC physical design team for ASIC chip synthesis
Focus on block synthesis to sign off timing and improve synthesis netlist quality
co-work with PD owners to improve place's QoR.
Requirements:
MS major in EE or related;
skilled with EDA tools such as DC(DCT), ICC/ICC2, Formality and PrimeTime;
Familiar with general IC design flow and physical design flow;
Familiar with Linux, skill in scripts including perl/tcl/cshell/python is a plus;
Good communication skills, proactive and team work;
Good spoken and written English;