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本岗位为实习生岗位,我们更期待2019/2020毕业的硕士研究生/本科生应聘此岗位。
This is the internship position, Master/Bachelor graduates in 2019/2020 will be preferred.
At Micron, we transform how the world uses information to enrich life. The pace is fast, collaboration occurs on a regular basis, and innovation is expected. As an IC Layout Design Engineer at Micron's Shanghai Design Center, you will work in a highly innovative and motivated design team using state of the art memory technologies to advance DRAM Memory design.
As part of a multi-disciplinary team, you will contribute to physical layout floor plan of various memory chip circuit blocks, and perform block level layout, LVS/DRC verification and using other CAD tools to check layout.
Of course, you will also work closely with Micron's various design teams in US and other countries and leverage vast resources available throughout Micron’s global sites. Additionally, you will perform verification (LVS/DRC etc.) of layout to the full-chip level, and assist in project tape out.
Requirements
College degree (or above) in Integrated Circuit Design and Electrical Engineering or other related engineering field.
Willing to develop his/her future career in IC layout
Hands-on and willing to learn
Familiar with Cadence OA and Calibre verification tools is a plus.
Understanding of basic CMOS circuits is a plus.
Score requirement: passed all the tests not including makeup score.
English language skill in writing and speaking.
CET4 score above 425 is a plus.
Has good communication and team work spirit