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Department: Central Engineering
Job Description
ASIC design engineer responsible forthe design, verification and evaluation of digital circuits in high
speed datacommunication ICs. The candidate will be involved in engineering implementationspec
writing from system requirements, RTL design, verification, synthesis,static timing analysis.
Job Requirement
MS or PD in EE or CE with VLSI emphasis.Graduate from reputable university with competitive GPA
or class ranking.Graduate course work in VLSI design, digital circuit theory, logic synthesis,logic
design or computer architecture. Exposure to graduate school projects inASIC design.
Musthave good knowledge of ASIC design flow and UNIX-based EDA tools. Must have RTL
experience including specification, design, verification and synthesis.
Mustbe proficient in the following skills:
Fundamental concepts in digital logic design
Concepts digital logic timing analysis
Verilog/VHDL coding and Lint tools
Strong Perl and Tcl scripting skill
Highlydesirable skills:
Synthesis using Synopsys or Cadence tools
Timing analysis using Primetime
DFT concepts of Scan, BIST
Formal verification
Low power design
MATLAB and C/C++ based system simulation andevaluation
DSP function hardware implementation such asdigital filter, equalizer, timing recovery functions
Circuit level or custom design experience
Goodpersonal communication skills and team working spirit. Hardworking andmotivated to be part of a highly competent design team.